In communication protocols, packet boundaries are often indicated by means of special patterns or flags. In a system using such a protocol, a flag detector/packet identifier is used to recognize flags and thus identify packets by their boundaries within a received stream of data.
Conventionally, a serial architecture is used with a bit-oriented protocol to identify flags in the received data. In these systems, flags are detected by processing a serial stream of data one bit at a time and by using "shift and compare" techniques. This serial architecture has several limitations.
First, unless sophisticated high speed logic is used, system speed is limited by the speed of serial logic technology. For example, for Advanced Schottky TTL logic, the processing speed may be between 50 and 70 megahertz. This constraint may make the flag detector a bottleneck for systems where packet communications take place over high speed links.
Second, conventional serial architecture only operates in a single channel mode. Because flag detection is a sequential bit by bit process, it generally operates on a single packet of data at a time. Thus, in a system which uses a high-speed link carrying multiple data channels according to a time division multiplexed (TDM) format, a separate flag detector may be used to process data arriving on each channel. This greatly increases the cost and complexity of the data link interface and diminishes the flexibility for systems in which the number of channels may vary.